1. Field of the Invention
The present invention relates to a semiconductor device having a pair of chip select terminals, and more particularly to a semiconductor device having a decoding circuit for selecting chips in a multiple-chip module.
2. Description of the Prior Art
Generally, to extend storage capacity in a semiconductor memory device, there are two methods. One is to increase the amount of data (that is, the number of bits in one word) to be inputted and outputted to/from the memory device. The other is to increase the number of addresses in order to designate locations of information to be stored in the memory device.
In the methods, the former requires allocation of one chip select terminal in which respective chip select terminals of memory chips are combined with each other. Because of use of such one chip select terminal, it has been impossible to allocate two chip select terminals in order to select such chips.
The latter requires a plurality of complicated chip selecting circuits such as decoders due to a shared data bus for chip select terminals of memory chips. For example, it is necessary to use decoders corresponding to the number of log N N in order to select chips, when the number of chips is N. Also, since such decoders are respectively located outside semiconductor chips, there is a problem that in packaging semiconductor chips a high-density integration is lowered.
Also, a technique to enable reduction of the number of terminals of a semiconductor device is disclosed in U.S. Pat. No. 4,760,291. Since this technique also requires a delay circuit for selecting chips, processing time to access information in a semiconductor device, such as access time and delay time and so on is delayed.